The present invention relates to the field of chip carriers and bus architecture. More specifically, the invention relates to a multi-chip carrier for connection to a multi-segmented pipeline bus and its method of operation.
Large electronic devices such as computers typically include a plurality of individual integrated circuits or chips which must be interconnected for communication between the chips. Typically, each chip is mounted in a chip carrier which is connected to one or more buses. The buses may be either a private bus in which all the components connected to the private bus are either the recipient or source of all the signals on the bus, or a shared bus. A shared bus may carry signals which, at any given time, are not being sent to or received from some of the chips connected to the bus. Rather, communication to or from the various connected chips is placed on the bus and each chip is provided with a device for determining whether the particular signal is pertinent to its operation. The present invention is concerned with shared bus systems.
Communication systems can be unsegmented or multi-segmented. In unsegmented systems, a signal, once placed on the bus, propagates the length of the bus without a delay other than that required by the electrical characteristics of the bus and the connections thereto. In a segmented system, one or more registers are provided for holding a signal for a period of time. Thus, a signal will propagate on a first segment until it reaches a holding register where it will be held for a period of time. Later, the signal will be sent from the register to the next segment where it will propagate until reaching the termination of the bus or another register. When the signal is unusable by components which are attached to the bus during the period in which it is held in a register, such period is referred to below as the latency period of the bus.